RISC (Reduced Instruction Set Computer)

A processor architecture that shifts the analytical process of a computational task from the execution or runtime to the preparation or compile time. By using less hardware or logic, the system can operate at higher speeds. RISC cuts down on the number and complexity of instructions, on the theory that each one can be accessed and executed faster, and that less semiconductor real estate is required to process them. The result is that for any given semiconductor technology, a more powerful microprocessor can be produced with RISC than with complex instruction set computer (CISC) architectures.

This simplification of computer instruction sets gains processing efficiencies. That theme works because all computers and programs execute mostly simple instructions. RISC has five design principles:

• Single-cycle execution — In most traditional central processing unit (CPU) designs, the peak possible execution rate is one instruction per basic machine cycle, and for a given technology, the cycle time has some fixed lower limit. Even on complex CPUs, most compiler-generated instructions are simple. RISC designs emphasize single-cycle execution, even at the expense of synthesizing multi-instruction sequences for some less-frequent operations.

• Hard-wired control, little or no microcode — Microcode adds a layer of interpretive overhead, raising the number of cycles per instruction, so even the simplest instructions can require several cycles.

• Simple instructions, few addressing modes — Complex instructions and addressing modes, which entail microcode or multicycle instructions, are avoided.

• Load and store, register-register design — Only loads and stores access memory; all others perform register-register operations. This tends to follow from the previous three principles.

• Efficient, deep pipelining — To make convenient use of hardware parallelism without the complexities of horizontal microcode, fast CPUs use pipelining. An n-stage pipeline keeps up to “n” instructions active at once, ideally finishing one (and starting another) every cycle. The instruction set must be carefully tuned to support pipelining.

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